CV

Education

• M.S. in Integrated Circuit Engineering, Southeast University, 2028 (expected)
• B.E. in Integrated Circuit Design and Integrated Systems, Xi’an University of Posts and Telecommunications, 2024

Research experience

• Design and Implementation of a Blink Detection Circuit Based on the Inter-frame Difference Method
  • Undergraduate Thesis Project, Dec. 2023 – Jun. 2024
  • Developed a hardware-based blink detection system to address fatigue driving by monitoring blink frequency in real-time.
  • Researched and optimized the inter-frame difference algorithm for low-latency hardware acceleration.
  • Designed the complete digital logic in Verilog and performed functional simulations to ensure timing closure.
  • Integrated a hardware pipeline involving OV5640 camera data acquisition, FPGA-based image processing, and real-time LCD display.
  • Implemented real-time features including fatigue level calculation, bounding box marking, and status visualization on FPGA.
  • Supervisor: Yu Liu
• Design of a 5-Stage Pipelined Processor Based on RISC-V Architecture
  • Digital System Design Project, Dec. 2022 – Jan. 2023
  • Designed and verified a synthesizable 32-bit pipelined CPU supporting R, I, S, U, and J-type instruction sets.
  • Developed a standard 5-stage pipeline architecture (IF, ID, EXE, MEM, WB) using Verilog.
  • Implemented core modules including the Instruction/Data Memory, ALU, Register File, and Control Unit.
  • Supported 20 instructions and successfully resolved data and control hazards through Data Forwarding and Static Branch Prediction.
  • Completed the hardware-in-the-loop verification by deploying and testing the design on an FPGA development board.

Honors and Awards

• First-class Academic Scholarship, XUPT, 2021 – 2023
• First Prize, National Mathematics Competition for College Students, 2023
• Second Prize, National English Competition for College Students, 2022
• Outstanding Volunteer, 2021

Skills

• Hardware Description & Programming
  • HDL: Verilog
  • Languages: Python, C/C++, Tcl
• Digital IC Design
  • Simulation: Mentor Graphics ModelSim, HSpice
  • Synthesis & Timing: Synopsys Design Compiler, PrimeTime
  • Implementation: Cadence Innovus
• FPGA Development
  • Xilinx Vivado